/***************************************************************************//**
* \file cyreg_pass.h
*
* \brief
* PASS register definition header
*
* \note
* Generator version: 1.6.0.481
* Database revision: TVIIBH4M_PR3_0
*
********************************************************************************
* \copyright
* Copyright 2016-2021, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_PASS_H_
#define _CYREG_PASS_H_

#include "cyip_pass.h"

/**
  * \brief Channel structure (PASS_SAR_CH0)
  */
#define CYREG_PASS0_SAR0_CH0_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900800UL)
#define CYREG_PASS0_SAR0_CH0_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900804UL)
#define CYREG_PASS0_SAR0_CH0_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900808UL)
#define CYREG_PASS0_SAR0_CH0_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090080CUL)
#define CYREG_PASS0_SAR0_CH0_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900810UL)
#define CYREG_PASS0_SAR0_CH0_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900814UL)
#define CYREG_PASS0_SAR0_CH0_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900818UL)
#define CYREG_PASS0_SAR0_CH0_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090081CUL)
#define CYREG_PASS0_SAR0_CH0_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900820UL)
#define CYREG_PASS0_SAR0_CH0_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900824UL)
#define CYREG_PASS0_SAR0_CH0_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900828UL)
#define CYREG_PASS0_SAR0_CH0_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900838UL)
#define CYREG_PASS0_SAR0_CH0_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090083CUL)

/**
  * \brief Channel structure (PASS_SAR_CH1)
  */
#define CYREG_PASS0_SAR0_CH1_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900840UL)
#define CYREG_PASS0_SAR0_CH1_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900844UL)
#define CYREG_PASS0_SAR0_CH1_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900848UL)
#define CYREG_PASS0_SAR0_CH1_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090084CUL)
#define CYREG_PASS0_SAR0_CH1_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900850UL)
#define CYREG_PASS0_SAR0_CH1_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900854UL)
#define CYREG_PASS0_SAR0_CH1_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900858UL)
#define CYREG_PASS0_SAR0_CH1_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090085CUL)
#define CYREG_PASS0_SAR0_CH1_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900860UL)
#define CYREG_PASS0_SAR0_CH1_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900864UL)
#define CYREG_PASS0_SAR0_CH1_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900868UL)
#define CYREG_PASS0_SAR0_CH1_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900878UL)
#define CYREG_PASS0_SAR0_CH1_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090087CUL)

/**
  * \brief Channel structure (PASS_SAR_CH2)
  */
#define CYREG_PASS0_SAR0_CH2_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900880UL)
#define CYREG_PASS0_SAR0_CH2_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900884UL)
#define CYREG_PASS0_SAR0_CH2_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900888UL)
#define CYREG_PASS0_SAR0_CH2_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090088CUL)
#define CYREG_PASS0_SAR0_CH2_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900890UL)
#define CYREG_PASS0_SAR0_CH2_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900894UL)
#define CYREG_PASS0_SAR0_CH2_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900898UL)
#define CYREG_PASS0_SAR0_CH2_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090089CUL)
#define CYREG_PASS0_SAR0_CH2_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409008A0UL)
#define CYREG_PASS0_SAR0_CH2_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409008A4UL)
#define CYREG_PASS0_SAR0_CH2_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409008A8UL)
#define CYREG_PASS0_SAR0_CH2_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409008B8UL)
#define CYREG_PASS0_SAR0_CH2_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409008BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH3)
  */
#define CYREG_PASS0_SAR0_CH3_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409008C0UL)
#define CYREG_PASS0_SAR0_CH3_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409008C4UL)
#define CYREG_PASS0_SAR0_CH3_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409008C8UL)
#define CYREG_PASS0_SAR0_CH3_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409008CCUL)
#define CYREG_PASS0_SAR0_CH3_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409008D0UL)
#define CYREG_PASS0_SAR0_CH3_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409008D4UL)
#define CYREG_PASS0_SAR0_CH3_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409008D8UL)
#define CYREG_PASS0_SAR0_CH3_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409008DCUL)
#define CYREG_PASS0_SAR0_CH3_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409008E0UL)
#define CYREG_PASS0_SAR0_CH3_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409008E4UL)
#define CYREG_PASS0_SAR0_CH3_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409008E8UL)
#define CYREG_PASS0_SAR0_CH3_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409008F8UL)
#define CYREG_PASS0_SAR0_CH3_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409008FCUL)

/**
  * \brief Channel structure (PASS_SAR_CH4)
  */
#define CYREG_PASS0_SAR0_CH4_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900900UL)
#define CYREG_PASS0_SAR0_CH4_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900904UL)
#define CYREG_PASS0_SAR0_CH4_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900908UL)
#define CYREG_PASS0_SAR0_CH4_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090090CUL)
#define CYREG_PASS0_SAR0_CH4_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900910UL)
#define CYREG_PASS0_SAR0_CH4_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900914UL)
#define CYREG_PASS0_SAR0_CH4_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900918UL)
#define CYREG_PASS0_SAR0_CH4_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090091CUL)
#define CYREG_PASS0_SAR0_CH4_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900920UL)
#define CYREG_PASS0_SAR0_CH4_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900924UL)
#define CYREG_PASS0_SAR0_CH4_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900928UL)
#define CYREG_PASS0_SAR0_CH4_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900938UL)
#define CYREG_PASS0_SAR0_CH4_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090093CUL)

/**
  * \brief Channel structure (PASS_SAR_CH5)
  */
#define CYREG_PASS0_SAR0_CH5_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900940UL)
#define CYREG_PASS0_SAR0_CH5_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900944UL)
#define CYREG_PASS0_SAR0_CH5_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900948UL)
#define CYREG_PASS0_SAR0_CH5_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090094CUL)
#define CYREG_PASS0_SAR0_CH5_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900950UL)
#define CYREG_PASS0_SAR0_CH5_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900954UL)
#define CYREG_PASS0_SAR0_CH5_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900958UL)
#define CYREG_PASS0_SAR0_CH5_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090095CUL)
#define CYREG_PASS0_SAR0_CH5_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900960UL)
#define CYREG_PASS0_SAR0_CH5_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900964UL)
#define CYREG_PASS0_SAR0_CH5_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900968UL)
#define CYREG_PASS0_SAR0_CH5_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900978UL)
#define CYREG_PASS0_SAR0_CH5_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090097CUL)

/**
  * \brief Channel structure (PASS_SAR_CH6)
  */
#define CYREG_PASS0_SAR0_CH6_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900980UL)
#define CYREG_PASS0_SAR0_CH6_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900984UL)
#define CYREG_PASS0_SAR0_CH6_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900988UL)
#define CYREG_PASS0_SAR0_CH6_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090098CUL)
#define CYREG_PASS0_SAR0_CH6_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900990UL)
#define CYREG_PASS0_SAR0_CH6_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900994UL)
#define CYREG_PASS0_SAR0_CH6_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900998UL)
#define CYREG_PASS0_SAR0_CH6_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090099CUL)
#define CYREG_PASS0_SAR0_CH6_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409009A0UL)
#define CYREG_PASS0_SAR0_CH6_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409009A4UL)
#define CYREG_PASS0_SAR0_CH6_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409009A8UL)
#define CYREG_PASS0_SAR0_CH6_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409009B8UL)
#define CYREG_PASS0_SAR0_CH6_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409009BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH7)
  */
#define CYREG_PASS0_SAR0_CH7_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409009C0UL)
#define CYREG_PASS0_SAR0_CH7_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409009C4UL)
#define CYREG_PASS0_SAR0_CH7_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409009C8UL)
#define CYREG_PASS0_SAR0_CH7_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409009CCUL)
#define CYREG_PASS0_SAR0_CH7_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409009D0UL)
#define CYREG_PASS0_SAR0_CH7_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409009D4UL)
#define CYREG_PASS0_SAR0_CH7_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409009D8UL)
#define CYREG_PASS0_SAR0_CH7_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409009DCUL)
#define CYREG_PASS0_SAR0_CH7_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409009E0UL)
#define CYREG_PASS0_SAR0_CH7_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409009E4UL)
#define CYREG_PASS0_SAR0_CH7_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409009E8UL)
#define CYREG_PASS0_SAR0_CH7_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409009F8UL)
#define CYREG_PASS0_SAR0_CH7_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409009FCUL)

/**
  * \brief Channel structure (PASS_SAR_CH8)
  */
#define CYREG_PASS0_SAR0_CH8_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900A00UL)
#define CYREG_PASS0_SAR0_CH8_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900A04UL)
#define CYREG_PASS0_SAR0_CH8_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900A08UL)
#define CYREG_PASS0_SAR0_CH8_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900A0CUL)
#define CYREG_PASS0_SAR0_CH8_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900A10UL)
#define CYREG_PASS0_SAR0_CH8_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900A14UL)
#define CYREG_PASS0_SAR0_CH8_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900A18UL)
#define CYREG_PASS0_SAR0_CH8_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900A1CUL)
#define CYREG_PASS0_SAR0_CH8_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900A20UL)
#define CYREG_PASS0_SAR0_CH8_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900A24UL)
#define CYREG_PASS0_SAR0_CH8_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900A28UL)
#define CYREG_PASS0_SAR0_CH8_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900A38UL)
#define CYREG_PASS0_SAR0_CH8_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900A3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH9)
  */
#define CYREG_PASS0_SAR0_CH9_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900A40UL)
#define CYREG_PASS0_SAR0_CH9_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900A44UL)
#define CYREG_PASS0_SAR0_CH9_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900A48UL)
#define CYREG_PASS0_SAR0_CH9_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900A4CUL)
#define CYREG_PASS0_SAR0_CH9_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900A50UL)
#define CYREG_PASS0_SAR0_CH9_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900A54UL)
#define CYREG_PASS0_SAR0_CH9_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900A58UL)
#define CYREG_PASS0_SAR0_CH9_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900A5CUL)
#define CYREG_PASS0_SAR0_CH9_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900A60UL)
#define CYREG_PASS0_SAR0_CH9_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900A64UL)
#define CYREG_PASS0_SAR0_CH9_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900A68UL)
#define CYREG_PASS0_SAR0_CH9_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900A78UL)
#define CYREG_PASS0_SAR0_CH9_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900A7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH10)
  */
#define CYREG_PASS0_SAR0_CH10_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900A80UL)
#define CYREG_PASS0_SAR0_CH10_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900A84UL)
#define CYREG_PASS0_SAR0_CH10_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900A88UL)
#define CYREG_PASS0_SAR0_CH10_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900A8CUL)
#define CYREG_PASS0_SAR0_CH10_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900A90UL)
#define CYREG_PASS0_SAR0_CH10_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900A94UL)
#define CYREG_PASS0_SAR0_CH10_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900A98UL)
#define CYREG_PASS0_SAR0_CH10_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900A9CUL)
#define CYREG_PASS0_SAR0_CH10_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900AA0UL)
#define CYREG_PASS0_SAR0_CH10_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900AA4UL)
#define CYREG_PASS0_SAR0_CH10_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900AA8UL)
#define CYREG_PASS0_SAR0_CH10_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900AB8UL)
#define CYREG_PASS0_SAR0_CH10_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900ABCUL)

/**
  * \brief Channel structure (PASS_SAR_CH11)
  */
#define CYREG_PASS0_SAR0_CH11_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900AC0UL)
#define CYREG_PASS0_SAR0_CH11_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900AC4UL)
#define CYREG_PASS0_SAR0_CH11_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900AC8UL)
#define CYREG_PASS0_SAR0_CH11_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900ACCUL)
#define CYREG_PASS0_SAR0_CH11_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900AD0UL)
#define CYREG_PASS0_SAR0_CH11_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900AD4UL)
#define CYREG_PASS0_SAR0_CH11_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900AD8UL)
#define CYREG_PASS0_SAR0_CH11_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900ADCUL)
#define CYREG_PASS0_SAR0_CH11_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900AE0UL)
#define CYREG_PASS0_SAR0_CH11_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900AE4UL)
#define CYREG_PASS0_SAR0_CH11_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900AE8UL)
#define CYREG_PASS0_SAR0_CH11_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900AF8UL)
#define CYREG_PASS0_SAR0_CH11_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900AFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH12)
  */
#define CYREG_PASS0_SAR0_CH12_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900B00UL)
#define CYREG_PASS0_SAR0_CH12_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900B04UL)
#define CYREG_PASS0_SAR0_CH12_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900B08UL)
#define CYREG_PASS0_SAR0_CH12_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900B0CUL)
#define CYREG_PASS0_SAR0_CH12_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900B10UL)
#define CYREG_PASS0_SAR0_CH12_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900B14UL)
#define CYREG_PASS0_SAR0_CH12_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900B18UL)
#define CYREG_PASS0_SAR0_CH12_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900B1CUL)
#define CYREG_PASS0_SAR0_CH12_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900B20UL)
#define CYREG_PASS0_SAR0_CH12_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900B24UL)
#define CYREG_PASS0_SAR0_CH12_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900B28UL)
#define CYREG_PASS0_SAR0_CH12_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900B38UL)
#define CYREG_PASS0_SAR0_CH12_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900B3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH13)
  */
#define CYREG_PASS0_SAR0_CH13_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900B40UL)
#define CYREG_PASS0_SAR0_CH13_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900B44UL)
#define CYREG_PASS0_SAR0_CH13_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900B48UL)
#define CYREG_PASS0_SAR0_CH13_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900B4CUL)
#define CYREG_PASS0_SAR0_CH13_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900B50UL)
#define CYREG_PASS0_SAR0_CH13_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900B54UL)
#define CYREG_PASS0_SAR0_CH13_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900B58UL)
#define CYREG_PASS0_SAR0_CH13_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900B5CUL)
#define CYREG_PASS0_SAR0_CH13_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900B60UL)
#define CYREG_PASS0_SAR0_CH13_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900B64UL)
#define CYREG_PASS0_SAR0_CH13_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900B68UL)
#define CYREG_PASS0_SAR0_CH13_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900B78UL)
#define CYREG_PASS0_SAR0_CH13_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900B7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH14)
  */
#define CYREG_PASS0_SAR0_CH14_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900B80UL)
#define CYREG_PASS0_SAR0_CH14_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900B84UL)
#define CYREG_PASS0_SAR0_CH14_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900B88UL)
#define CYREG_PASS0_SAR0_CH14_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900B8CUL)
#define CYREG_PASS0_SAR0_CH14_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900B90UL)
#define CYREG_PASS0_SAR0_CH14_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900B94UL)
#define CYREG_PASS0_SAR0_CH14_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900B98UL)
#define CYREG_PASS0_SAR0_CH14_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900B9CUL)
#define CYREG_PASS0_SAR0_CH14_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900BA0UL)
#define CYREG_PASS0_SAR0_CH14_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900BA4UL)
#define CYREG_PASS0_SAR0_CH14_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900BA8UL)
#define CYREG_PASS0_SAR0_CH14_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900BB8UL)
#define CYREG_PASS0_SAR0_CH14_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900BBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH15)
  */
#define CYREG_PASS0_SAR0_CH15_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900BC0UL)
#define CYREG_PASS0_SAR0_CH15_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900BC4UL)
#define CYREG_PASS0_SAR0_CH15_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900BC8UL)
#define CYREG_PASS0_SAR0_CH15_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900BCCUL)
#define CYREG_PASS0_SAR0_CH15_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900BD0UL)
#define CYREG_PASS0_SAR0_CH15_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900BD4UL)
#define CYREG_PASS0_SAR0_CH15_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900BD8UL)
#define CYREG_PASS0_SAR0_CH15_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900BDCUL)
#define CYREG_PASS0_SAR0_CH15_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900BE0UL)
#define CYREG_PASS0_SAR0_CH15_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900BE4UL)
#define CYREG_PASS0_SAR0_CH15_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900BE8UL)
#define CYREG_PASS0_SAR0_CH15_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900BF8UL)
#define CYREG_PASS0_SAR0_CH15_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900BFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH16)
  */
#define CYREG_PASS0_SAR0_CH16_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900C00UL)
#define CYREG_PASS0_SAR0_CH16_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900C04UL)
#define CYREG_PASS0_SAR0_CH16_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900C08UL)
#define CYREG_PASS0_SAR0_CH16_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900C0CUL)
#define CYREG_PASS0_SAR0_CH16_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900C10UL)
#define CYREG_PASS0_SAR0_CH16_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900C14UL)
#define CYREG_PASS0_SAR0_CH16_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900C18UL)
#define CYREG_PASS0_SAR0_CH16_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900C1CUL)
#define CYREG_PASS0_SAR0_CH16_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900C20UL)
#define CYREG_PASS0_SAR0_CH16_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900C24UL)
#define CYREG_PASS0_SAR0_CH16_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900C28UL)
#define CYREG_PASS0_SAR0_CH16_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900C38UL)
#define CYREG_PASS0_SAR0_CH16_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900C3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH17)
  */
#define CYREG_PASS0_SAR0_CH17_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900C40UL)
#define CYREG_PASS0_SAR0_CH17_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900C44UL)
#define CYREG_PASS0_SAR0_CH17_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900C48UL)
#define CYREG_PASS0_SAR0_CH17_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900C4CUL)
#define CYREG_PASS0_SAR0_CH17_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900C50UL)
#define CYREG_PASS0_SAR0_CH17_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900C54UL)
#define CYREG_PASS0_SAR0_CH17_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900C58UL)
#define CYREG_PASS0_SAR0_CH17_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900C5CUL)
#define CYREG_PASS0_SAR0_CH17_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900C60UL)
#define CYREG_PASS0_SAR0_CH17_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900C64UL)
#define CYREG_PASS0_SAR0_CH17_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900C68UL)
#define CYREG_PASS0_SAR0_CH17_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900C78UL)
#define CYREG_PASS0_SAR0_CH17_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900C7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH18)
  */
#define CYREG_PASS0_SAR0_CH18_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900C80UL)
#define CYREG_PASS0_SAR0_CH18_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900C84UL)
#define CYREG_PASS0_SAR0_CH18_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900C88UL)
#define CYREG_PASS0_SAR0_CH18_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900C8CUL)
#define CYREG_PASS0_SAR0_CH18_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900C90UL)
#define CYREG_PASS0_SAR0_CH18_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900C94UL)
#define CYREG_PASS0_SAR0_CH18_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900C98UL)
#define CYREG_PASS0_SAR0_CH18_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900C9CUL)
#define CYREG_PASS0_SAR0_CH18_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900CA0UL)
#define CYREG_PASS0_SAR0_CH18_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900CA4UL)
#define CYREG_PASS0_SAR0_CH18_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900CA8UL)
#define CYREG_PASS0_SAR0_CH18_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900CB8UL)
#define CYREG_PASS0_SAR0_CH18_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900CBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH19)
  */
#define CYREG_PASS0_SAR0_CH19_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900CC0UL)
#define CYREG_PASS0_SAR0_CH19_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900CC4UL)
#define CYREG_PASS0_SAR0_CH19_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900CC8UL)
#define CYREG_PASS0_SAR0_CH19_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900CCCUL)
#define CYREG_PASS0_SAR0_CH19_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900CD0UL)
#define CYREG_PASS0_SAR0_CH19_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900CD4UL)
#define CYREG_PASS0_SAR0_CH19_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900CD8UL)
#define CYREG_PASS0_SAR0_CH19_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900CDCUL)
#define CYREG_PASS0_SAR0_CH19_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900CE0UL)
#define CYREG_PASS0_SAR0_CH19_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900CE4UL)
#define CYREG_PASS0_SAR0_CH19_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900CE8UL)
#define CYREG_PASS0_SAR0_CH19_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900CF8UL)
#define CYREG_PASS0_SAR0_CH19_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900CFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH20)
  */
#define CYREG_PASS0_SAR0_CH20_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900D00UL)
#define CYREG_PASS0_SAR0_CH20_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900D04UL)
#define CYREG_PASS0_SAR0_CH20_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900D08UL)
#define CYREG_PASS0_SAR0_CH20_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900D0CUL)
#define CYREG_PASS0_SAR0_CH20_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900D10UL)
#define CYREG_PASS0_SAR0_CH20_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900D14UL)
#define CYREG_PASS0_SAR0_CH20_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900D18UL)
#define CYREG_PASS0_SAR0_CH20_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900D1CUL)
#define CYREG_PASS0_SAR0_CH20_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900D20UL)
#define CYREG_PASS0_SAR0_CH20_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900D24UL)
#define CYREG_PASS0_SAR0_CH20_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900D28UL)
#define CYREG_PASS0_SAR0_CH20_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900D38UL)
#define CYREG_PASS0_SAR0_CH20_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900D3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH21)
  */
#define CYREG_PASS0_SAR0_CH21_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900D40UL)
#define CYREG_PASS0_SAR0_CH21_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900D44UL)
#define CYREG_PASS0_SAR0_CH21_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900D48UL)
#define CYREG_PASS0_SAR0_CH21_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900D4CUL)
#define CYREG_PASS0_SAR0_CH21_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900D50UL)
#define CYREG_PASS0_SAR0_CH21_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900D54UL)
#define CYREG_PASS0_SAR0_CH21_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900D58UL)
#define CYREG_PASS0_SAR0_CH21_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900D5CUL)
#define CYREG_PASS0_SAR0_CH21_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900D60UL)
#define CYREG_PASS0_SAR0_CH21_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900D64UL)
#define CYREG_PASS0_SAR0_CH21_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900D68UL)
#define CYREG_PASS0_SAR0_CH21_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900D78UL)
#define CYREG_PASS0_SAR0_CH21_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900D7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH22)
  */
#define CYREG_PASS0_SAR0_CH22_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900D80UL)
#define CYREG_PASS0_SAR0_CH22_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900D84UL)
#define CYREG_PASS0_SAR0_CH22_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900D88UL)
#define CYREG_PASS0_SAR0_CH22_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900D8CUL)
#define CYREG_PASS0_SAR0_CH22_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900D90UL)
#define CYREG_PASS0_SAR0_CH22_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900D94UL)
#define CYREG_PASS0_SAR0_CH22_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900D98UL)
#define CYREG_PASS0_SAR0_CH22_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900D9CUL)
#define CYREG_PASS0_SAR0_CH22_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900DA0UL)
#define CYREG_PASS0_SAR0_CH22_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900DA4UL)
#define CYREG_PASS0_SAR0_CH22_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900DA8UL)
#define CYREG_PASS0_SAR0_CH22_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900DB8UL)
#define CYREG_PASS0_SAR0_CH22_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900DBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH23)
  */
#define CYREG_PASS0_SAR0_CH23_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900DC0UL)
#define CYREG_PASS0_SAR0_CH23_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900DC4UL)
#define CYREG_PASS0_SAR0_CH23_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900DC8UL)
#define CYREG_PASS0_SAR0_CH23_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900DCCUL)
#define CYREG_PASS0_SAR0_CH23_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900DD0UL)
#define CYREG_PASS0_SAR0_CH23_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900DD4UL)
#define CYREG_PASS0_SAR0_CH23_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900DD8UL)
#define CYREG_PASS0_SAR0_CH23_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900DDCUL)
#define CYREG_PASS0_SAR0_CH23_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900DE0UL)
#define CYREG_PASS0_SAR0_CH23_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900DE4UL)
#define CYREG_PASS0_SAR0_CH23_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900DE8UL)
#define CYREG_PASS0_SAR0_CH23_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900DF8UL)
#define CYREG_PASS0_SAR0_CH23_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900DFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH24)
  */
#define CYREG_PASS0_SAR0_CH24_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900E00UL)
#define CYREG_PASS0_SAR0_CH24_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900E04UL)
#define CYREG_PASS0_SAR0_CH24_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900E08UL)
#define CYREG_PASS0_SAR0_CH24_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900E0CUL)
#define CYREG_PASS0_SAR0_CH24_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900E10UL)
#define CYREG_PASS0_SAR0_CH24_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900E14UL)
#define CYREG_PASS0_SAR0_CH24_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900E18UL)
#define CYREG_PASS0_SAR0_CH24_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900E1CUL)
#define CYREG_PASS0_SAR0_CH24_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900E20UL)
#define CYREG_PASS0_SAR0_CH24_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900E24UL)
#define CYREG_PASS0_SAR0_CH24_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900E28UL)
#define CYREG_PASS0_SAR0_CH24_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900E38UL)
#define CYREG_PASS0_SAR0_CH24_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900E3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH25)
  */
#define CYREG_PASS0_SAR0_CH25_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900E40UL)
#define CYREG_PASS0_SAR0_CH25_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900E44UL)
#define CYREG_PASS0_SAR0_CH25_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900E48UL)
#define CYREG_PASS0_SAR0_CH25_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900E4CUL)
#define CYREG_PASS0_SAR0_CH25_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900E50UL)
#define CYREG_PASS0_SAR0_CH25_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900E54UL)
#define CYREG_PASS0_SAR0_CH25_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900E58UL)
#define CYREG_PASS0_SAR0_CH25_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900E5CUL)
#define CYREG_PASS0_SAR0_CH25_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900E60UL)
#define CYREG_PASS0_SAR0_CH25_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900E64UL)
#define CYREG_PASS0_SAR0_CH25_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900E68UL)
#define CYREG_PASS0_SAR0_CH25_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900E78UL)
#define CYREG_PASS0_SAR0_CH25_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900E7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH26)
  */
#define CYREG_PASS0_SAR0_CH26_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900E80UL)
#define CYREG_PASS0_SAR0_CH26_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900E84UL)
#define CYREG_PASS0_SAR0_CH26_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900E88UL)
#define CYREG_PASS0_SAR0_CH26_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900E8CUL)
#define CYREG_PASS0_SAR0_CH26_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900E90UL)
#define CYREG_PASS0_SAR0_CH26_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900E94UL)
#define CYREG_PASS0_SAR0_CH26_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900E98UL)
#define CYREG_PASS0_SAR0_CH26_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900E9CUL)
#define CYREG_PASS0_SAR0_CH26_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900EA0UL)
#define CYREG_PASS0_SAR0_CH26_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900EA4UL)
#define CYREG_PASS0_SAR0_CH26_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900EA8UL)
#define CYREG_PASS0_SAR0_CH26_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900EB8UL)
#define CYREG_PASS0_SAR0_CH26_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900EBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH27)
  */
#define CYREG_PASS0_SAR0_CH27_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900EC0UL)
#define CYREG_PASS0_SAR0_CH27_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900EC4UL)
#define CYREG_PASS0_SAR0_CH27_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900EC8UL)
#define CYREG_PASS0_SAR0_CH27_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900ECCUL)
#define CYREG_PASS0_SAR0_CH27_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900ED0UL)
#define CYREG_PASS0_SAR0_CH27_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900ED4UL)
#define CYREG_PASS0_SAR0_CH27_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900ED8UL)
#define CYREG_PASS0_SAR0_CH27_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900EDCUL)
#define CYREG_PASS0_SAR0_CH27_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900EE0UL)
#define CYREG_PASS0_SAR0_CH27_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900EE4UL)
#define CYREG_PASS0_SAR0_CH27_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900EE8UL)
#define CYREG_PASS0_SAR0_CH27_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900EF8UL)
#define CYREG_PASS0_SAR0_CH27_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900EFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH28)
  */
#define CYREG_PASS0_SAR0_CH28_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900F00UL)
#define CYREG_PASS0_SAR0_CH28_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900F04UL)
#define CYREG_PASS0_SAR0_CH28_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900F08UL)
#define CYREG_PASS0_SAR0_CH28_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900F0CUL)
#define CYREG_PASS0_SAR0_CH28_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900F10UL)
#define CYREG_PASS0_SAR0_CH28_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900F14UL)
#define CYREG_PASS0_SAR0_CH28_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900F18UL)
#define CYREG_PASS0_SAR0_CH28_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900F1CUL)
#define CYREG_PASS0_SAR0_CH28_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900F20UL)
#define CYREG_PASS0_SAR0_CH28_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900F24UL)
#define CYREG_PASS0_SAR0_CH28_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900F28UL)
#define CYREG_PASS0_SAR0_CH28_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900F38UL)
#define CYREG_PASS0_SAR0_CH28_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900F3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH29)
  */
#define CYREG_PASS0_SAR0_CH29_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900F40UL)
#define CYREG_PASS0_SAR0_CH29_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900F44UL)
#define CYREG_PASS0_SAR0_CH29_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900F48UL)
#define CYREG_PASS0_SAR0_CH29_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900F4CUL)
#define CYREG_PASS0_SAR0_CH29_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900F50UL)
#define CYREG_PASS0_SAR0_CH29_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900F54UL)
#define CYREG_PASS0_SAR0_CH29_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900F58UL)
#define CYREG_PASS0_SAR0_CH29_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900F5CUL)
#define CYREG_PASS0_SAR0_CH29_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900F60UL)
#define CYREG_PASS0_SAR0_CH29_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900F64UL)
#define CYREG_PASS0_SAR0_CH29_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900F68UL)
#define CYREG_PASS0_SAR0_CH29_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900F78UL)
#define CYREG_PASS0_SAR0_CH29_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900F7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH30)
  */
#define CYREG_PASS0_SAR0_CH30_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900F80UL)
#define CYREG_PASS0_SAR0_CH30_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900F84UL)
#define CYREG_PASS0_SAR0_CH30_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900F88UL)
#define CYREG_PASS0_SAR0_CH30_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900F8CUL)
#define CYREG_PASS0_SAR0_CH30_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900F90UL)
#define CYREG_PASS0_SAR0_CH30_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900F94UL)
#define CYREG_PASS0_SAR0_CH30_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900F98UL)
#define CYREG_PASS0_SAR0_CH30_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900F9CUL)
#define CYREG_PASS0_SAR0_CH30_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900FA0UL)
#define CYREG_PASS0_SAR0_CH30_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900FA4UL)
#define CYREG_PASS0_SAR0_CH30_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900FA8UL)
#define CYREG_PASS0_SAR0_CH30_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900FB8UL)
#define CYREG_PASS0_SAR0_CH30_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900FBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH31)
  */
#define CYREG_PASS0_SAR0_CH31_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40900FC0UL)
#define CYREG_PASS0_SAR0_CH31_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40900FC4UL)
#define CYREG_PASS0_SAR0_CH31_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40900FC8UL)
#define CYREG_PASS0_SAR0_CH31_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40900FCCUL)
#define CYREG_PASS0_SAR0_CH31_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40900FD0UL)
#define CYREG_PASS0_SAR0_CH31_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40900FD4UL)
#define CYREG_PASS0_SAR0_CH31_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40900FD8UL)
#define CYREG_PASS0_SAR0_CH31_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40900FDCUL)
#define CYREG_PASS0_SAR0_CH31_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40900FE0UL)
#define CYREG_PASS0_SAR0_CH31_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40900FE4UL)
#define CYREG_PASS0_SAR0_CH31_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40900FE8UL)
#define CYREG_PASS0_SAR0_CH31_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40900FF8UL)
#define CYREG_PASS0_SAR0_CH31_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40900FFCUL)

/**
  * \brief SAR ADC with Sequencer for S40E (PASS_SAR0)
  */
#define CYREG_PASS0_SAR0_CTL            ((volatile un_PASS_SAR_CTL_t*) 0x40900000UL)
#define CYREG_PASS0_SAR0_DIAG_CTL       ((volatile un_PASS_SAR_DIAG_CTL_t*) 0x40900004UL)
#define CYREG_PASS0_SAR0_PRECOND_CTL    ((volatile un_PASS_SAR_PRECOND_CTL_t*) 0x40900010UL)
#define CYREG_PASS0_SAR0_ANA_CAL        ((volatile un_PASS_SAR_ANA_CAL_t*) 0x40900080UL)
#define CYREG_PASS0_SAR0_DIG_CAL        ((volatile un_PASS_SAR_DIG_CAL_t*) 0x40900084UL)
#define CYREG_PASS0_SAR0_ANA_CAL_ALT    ((volatile un_PASS_SAR_ANA_CAL_ALT_t*) 0x40900090UL)
#define CYREG_PASS0_SAR0_DIG_CAL_ALT    ((volatile un_PASS_SAR_DIG_CAL_ALT_t*) 0x40900094UL)
#define CYREG_PASS0_SAR0_CAL_UPD_CMD    ((volatile un_PASS_SAR_CAL_UPD_CMD_t*) 0x40900098UL)
#define CYREG_PASS0_SAR0_TR_PEND        ((volatile un_PASS_SAR_TR_PEND_t*) 0x40900100UL)
#define CYREG_PASS0_SAR0_WORK_VALID     ((volatile un_PASS_SAR_WORK_VALID_t*) 0x40900180UL)
#define CYREG_PASS0_SAR0_WORK_RANGE     ((volatile un_PASS_SAR_WORK_RANGE_t*) 0x40900184UL)
#define CYREG_PASS0_SAR0_WORK_RANGE_HI  ((volatile un_PASS_SAR_WORK_RANGE_HI_t*) 0x40900188UL)
#define CYREG_PASS0_SAR0_WORK_PULSE     ((volatile un_PASS_SAR_WORK_PULSE_t*) 0x4090018CUL)
#define CYREG_PASS0_SAR0_RESULT_VALID   ((volatile un_PASS_SAR_RESULT_VALID_t*) 0x409001A0UL)
#define CYREG_PASS0_SAR0_RESULT_RANGE_HI ((volatile un_PASS_SAR_RESULT_RANGE_HI_t*) 0x409001A4UL)
#define CYREG_PASS0_SAR0_STATUS         ((volatile un_PASS_SAR_STATUS_t*) 0x40900200UL)
#define CYREG_PASS0_SAR0_AVG_STAT       ((volatile un_PASS_SAR_AVG_STAT_t*) 0x40900204UL)

/**
  * \brief Channel structure (PASS_SAR_CH0)
  */
#define CYREG_PASS0_SAR1_CH0_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901800UL)
#define CYREG_PASS0_SAR1_CH0_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901804UL)
#define CYREG_PASS0_SAR1_CH0_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901808UL)
#define CYREG_PASS0_SAR1_CH0_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090180CUL)
#define CYREG_PASS0_SAR1_CH0_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901810UL)
#define CYREG_PASS0_SAR1_CH0_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901814UL)
#define CYREG_PASS0_SAR1_CH0_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901818UL)
#define CYREG_PASS0_SAR1_CH0_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090181CUL)
#define CYREG_PASS0_SAR1_CH0_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901820UL)
#define CYREG_PASS0_SAR1_CH0_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901824UL)
#define CYREG_PASS0_SAR1_CH0_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901828UL)
#define CYREG_PASS0_SAR1_CH0_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901838UL)
#define CYREG_PASS0_SAR1_CH0_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090183CUL)

/**
  * \brief Channel structure (PASS_SAR_CH1)
  */
#define CYREG_PASS0_SAR1_CH1_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901840UL)
#define CYREG_PASS0_SAR1_CH1_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901844UL)
#define CYREG_PASS0_SAR1_CH1_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901848UL)
#define CYREG_PASS0_SAR1_CH1_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090184CUL)
#define CYREG_PASS0_SAR1_CH1_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901850UL)
#define CYREG_PASS0_SAR1_CH1_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901854UL)
#define CYREG_PASS0_SAR1_CH1_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901858UL)
#define CYREG_PASS0_SAR1_CH1_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090185CUL)
#define CYREG_PASS0_SAR1_CH1_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901860UL)
#define CYREG_PASS0_SAR1_CH1_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901864UL)
#define CYREG_PASS0_SAR1_CH1_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901868UL)
#define CYREG_PASS0_SAR1_CH1_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901878UL)
#define CYREG_PASS0_SAR1_CH1_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090187CUL)

/**
  * \brief Channel structure (PASS_SAR_CH2)
  */
#define CYREG_PASS0_SAR1_CH2_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901880UL)
#define CYREG_PASS0_SAR1_CH2_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901884UL)
#define CYREG_PASS0_SAR1_CH2_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901888UL)
#define CYREG_PASS0_SAR1_CH2_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090188CUL)
#define CYREG_PASS0_SAR1_CH2_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901890UL)
#define CYREG_PASS0_SAR1_CH2_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901894UL)
#define CYREG_PASS0_SAR1_CH2_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901898UL)
#define CYREG_PASS0_SAR1_CH2_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090189CUL)
#define CYREG_PASS0_SAR1_CH2_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409018A0UL)
#define CYREG_PASS0_SAR1_CH2_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409018A4UL)
#define CYREG_PASS0_SAR1_CH2_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409018A8UL)
#define CYREG_PASS0_SAR1_CH2_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409018B8UL)
#define CYREG_PASS0_SAR1_CH2_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409018BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH3)
  */
#define CYREG_PASS0_SAR1_CH3_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409018C0UL)
#define CYREG_PASS0_SAR1_CH3_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409018C4UL)
#define CYREG_PASS0_SAR1_CH3_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409018C8UL)
#define CYREG_PASS0_SAR1_CH3_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409018CCUL)
#define CYREG_PASS0_SAR1_CH3_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409018D0UL)
#define CYREG_PASS0_SAR1_CH3_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409018D4UL)
#define CYREG_PASS0_SAR1_CH3_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409018D8UL)
#define CYREG_PASS0_SAR1_CH3_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409018DCUL)
#define CYREG_PASS0_SAR1_CH3_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409018E0UL)
#define CYREG_PASS0_SAR1_CH3_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409018E4UL)
#define CYREG_PASS0_SAR1_CH3_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409018E8UL)
#define CYREG_PASS0_SAR1_CH3_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409018F8UL)
#define CYREG_PASS0_SAR1_CH3_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409018FCUL)

/**
  * \brief Channel structure (PASS_SAR_CH4)
  */
#define CYREG_PASS0_SAR1_CH4_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901900UL)
#define CYREG_PASS0_SAR1_CH4_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901904UL)
#define CYREG_PASS0_SAR1_CH4_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901908UL)
#define CYREG_PASS0_SAR1_CH4_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090190CUL)
#define CYREG_PASS0_SAR1_CH4_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901910UL)
#define CYREG_PASS0_SAR1_CH4_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901914UL)
#define CYREG_PASS0_SAR1_CH4_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901918UL)
#define CYREG_PASS0_SAR1_CH4_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090191CUL)
#define CYREG_PASS0_SAR1_CH4_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901920UL)
#define CYREG_PASS0_SAR1_CH4_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901924UL)
#define CYREG_PASS0_SAR1_CH4_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901928UL)
#define CYREG_PASS0_SAR1_CH4_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901938UL)
#define CYREG_PASS0_SAR1_CH4_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090193CUL)

/**
  * \brief Channel structure (PASS_SAR_CH5)
  */
#define CYREG_PASS0_SAR1_CH5_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901940UL)
#define CYREG_PASS0_SAR1_CH5_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901944UL)
#define CYREG_PASS0_SAR1_CH5_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901948UL)
#define CYREG_PASS0_SAR1_CH5_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090194CUL)
#define CYREG_PASS0_SAR1_CH5_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901950UL)
#define CYREG_PASS0_SAR1_CH5_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901954UL)
#define CYREG_PASS0_SAR1_CH5_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901958UL)
#define CYREG_PASS0_SAR1_CH5_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090195CUL)
#define CYREG_PASS0_SAR1_CH5_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901960UL)
#define CYREG_PASS0_SAR1_CH5_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901964UL)
#define CYREG_PASS0_SAR1_CH5_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901968UL)
#define CYREG_PASS0_SAR1_CH5_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901978UL)
#define CYREG_PASS0_SAR1_CH5_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090197CUL)

/**
  * \brief Channel structure (PASS_SAR_CH6)
  */
#define CYREG_PASS0_SAR1_CH6_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901980UL)
#define CYREG_PASS0_SAR1_CH6_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901984UL)
#define CYREG_PASS0_SAR1_CH6_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901988UL)
#define CYREG_PASS0_SAR1_CH6_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090198CUL)
#define CYREG_PASS0_SAR1_CH6_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901990UL)
#define CYREG_PASS0_SAR1_CH6_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901994UL)
#define CYREG_PASS0_SAR1_CH6_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901998UL)
#define CYREG_PASS0_SAR1_CH6_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090199CUL)
#define CYREG_PASS0_SAR1_CH6_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409019A0UL)
#define CYREG_PASS0_SAR1_CH6_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409019A4UL)
#define CYREG_PASS0_SAR1_CH6_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409019A8UL)
#define CYREG_PASS0_SAR1_CH6_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409019B8UL)
#define CYREG_PASS0_SAR1_CH6_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409019BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH7)
  */
#define CYREG_PASS0_SAR1_CH7_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409019C0UL)
#define CYREG_PASS0_SAR1_CH7_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409019C4UL)
#define CYREG_PASS0_SAR1_CH7_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409019C8UL)
#define CYREG_PASS0_SAR1_CH7_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409019CCUL)
#define CYREG_PASS0_SAR1_CH7_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409019D0UL)
#define CYREG_PASS0_SAR1_CH7_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409019D4UL)
#define CYREG_PASS0_SAR1_CH7_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409019D8UL)
#define CYREG_PASS0_SAR1_CH7_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409019DCUL)
#define CYREG_PASS0_SAR1_CH7_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409019E0UL)
#define CYREG_PASS0_SAR1_CH7_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409019E4UL)
#define CYREG_PASS0_SAR1_CH7_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409019E8UL)
#define CYREG_PASS0_SAR1_CH7_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409019F8UL)
#define CYREG_PASS0_SAR1_CH7_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409019FCUL)

/**
  * \brief Channel structure (PASS_SAR_CH8)
  */
#define CYREG_PASS0_SAR1_CH8_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901A00UL)
#define CYREG_PASS0_SAR1_CH8_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901A04UL)
#define CYREG_PASS0_SAR1_CH8_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901A08UL)
#define CYREG_PASS0_SAR1_CH8_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901A0CUL)
#define CYREG_PASS0_SAR1_CH8_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901A10UL)
#define CYREG_PASS0_SAR1_CH8_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901A14UL)
#define CYREG_PASS0_SAR1_CH8_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901A18UL)
#define CYREG_PASS0_SAR1_CH8_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901A1CUL)
#define CYREG_PASS0_SAR1_CH8_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901A20UL)
#define CYREG_PASS0_SAR1_CH8_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901A24UL)
#define CYREG_PASS0_SAR1_CH8_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901A28UL)
#define CYREG_PASS0_SAR1_CH8_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901A38UL)
#define CYREG_PASS0_SAR1_CH8_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901A3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH9)
  */
#define CYREG_PASS0_SAR1_CH9_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901A40UL)
#define CYREG_PASS0_SAR1_CH9_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901A44UL)
#define CYREG_PASS0_SAR1_CH9_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901A48UL)
#define CYREG_PASS0_SAR1_CH9_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901A4CUL)
#define CYREG_PASS0_SAR1_CH9_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901A50UL)
#define CYREG_PASS0_SAR1_CH9_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901A54UL)
#define CYREG_PASS0_SAR1_CH9_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901A58UL)
#define CYREG_PASS0_SAR1_CH9_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901A5CUL)
#define CYREG_PASS0_SAR1_CH9_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901A60UL)
#define CYREG_PASS0_SAR1_CH9_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901A64UL)
#define CYREG_PASS0_SAR1_CH9_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901A68UL)
#define CYREG_PASS0_SAR1_CH9_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901A78UL)
#define CYREG_PASS0_SAR1_CH9_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901A7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH10)
  */
#define CYREG_PASS0_SAR1_CH10_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901A80UL)
#define CYREG_PASS0_SAR1_CH10_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901A84UL)
#define CYREG_PASS0_SAR1_CH10_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901A88UL)
#define CYREG_PASS0_SAR1_CH10_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901A8CUL)
#define CYREG_PASS0_SAR1_CH10_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901A90UL)
#define CYREG_PASS0_SAR1_CH10_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901A94UL)
#define CYREG_PASS0_SAR1_CH10_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901A98UL)
#define CYREG_PASS0_SAR1_CH10_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901A9CUL)
#define CYREG_PASS0_SAR1_CH10_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901AA0UL)
#define CYREG_PASS0_SAR1_CH10_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901AA4UL)
#define CYREG_PASS0_SAR1_CH10_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901AA8UL)
#define CYREG_PASS0_SAR1_CH10_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901AB8UL)
#define CYREG_PASS0_SAR1_CH10_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901ABCUL)

/**
  * \brief Channel structure (PASS_SAR_CH11)
  */
#define CYREG_PASS0_SAR1_CH11_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901AC0UL)
#define CYREG_PASS0_SAR1_CH11_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901AC4UL)
#define CYREG_PASS0_SAR1_CH11_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901AC8UL)
#define CYREG_PASS0_SAR1_CH11_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901ACCUL)
#define CYREG_PASS0_SAR1_CH11_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901AD0UL)
#define CYREG_PASS0_SAR1_CH11_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901AD4UL)
#define CYREG_PASS0_SAR1_CH11_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901AD8UL)
#define CYREG_PASS0_SAR1_CH11_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901ADCUL)
#define CYREG_PASS0_SAR1_CH11_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901AE0UL)
#define CYREG_PASS0_SAR1_CH11_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901AE4UL)
#define CYREG_PASS0_SAR1_CH11_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901AE8UL)
#define CYREG_PASS0_SAR1_CH11_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901AF8UL)
#define CYREG_PASS0_SAR1_CH11_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901AFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH12)
  */
#define CYREG_PASS0_SAR1_CH12_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901B00UL)
#define CYREG_PASS0_SAR1_CH12_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901B04UL)
#define CYREG_PASS0_SAR1_CH12_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901B08UL)
#define CYREG_PASS0_SAR1_CH12_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901B0CUL)
#define CYREG_PASS0_SAR1_CH12_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901B10UL)
#define CYREG_PASS0_SAR1_CH12_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901B14UL)
#define CYREG_PASS0_SAR1_CH12_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901B18UL)
#define CYREG_PASS0_SAR1_CH12_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901B1CUL)
#define CYREG_PASS0_SAR1_CH12_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901B20UL)
#define CYREG_PASS0_SAR1_CH12_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901B24UL)
#define CYREG_PASS0_SAR1_CH12_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901B28UL)
#define CYREG_PASS0_SAR1_CH12_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901B38UL)
#define CYREG_PASS0_SAR1_CH12_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901B3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH13)
  */
#define CYREG_PASS0_SAR1_CH13_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901B40UL)
#define CYREG_PASS0_SAR1_CH13_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901B44UL)
#define CYREG_PASS0_SAR1_CH13_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901B48UL)
#define CYREG_PASS0_SAR1_CH13_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901B4CUL)
#define CYREG_PASS0_SAR1_CH13_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901B50UL)
#define CYREG_PASS0_SAR1_CH13_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901B54UL)
#define CYREG_PASS0_SAR1_CH13_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901B58UL)
#define CYREG_PASS0_SAR1_CH13_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901B5CUL)
#define CYREG_PASS0_SAR1_CH13_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901B60UL)
#define CYREG_PASS0_SAR1_CH13_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901B64UL)
#define CYREG_PASS0_SAR1_CH13_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901B68UL)
#define CYREG_PASS0_SAR1_CH13_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901B78UL)
#define CYREG_PASS0_SAR1_CH13_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901B7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH14)
  */
#define CYREG_PASS0_SAR1_CH14_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901B80UL)
#define CYREG_PASS0_SAR1_CH14_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901B84UL)
#define CYREG_PASS0_SAR1_CH14_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901B88UL)
#define CYREG_PASS0_SAR1_CH14_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901B8CUL)
#define CYREG_PASS0_SAR1_CH14_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901B90UL)
#define CYREG_PASS0_SAR1_CH14_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901B94UL)
#define CYREG_PASS0_SAR1_CH14_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901B98UL)
#define CYREG_PASS0_SAR1_CH14_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901B9CUL)
#define CYREG_PASS0_SAR1_CH14_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901BA0UL)
#define CYREG_PASS0_SAR1_CH14_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901BA4UL)
#define CYREG_PASS0_SAR1_CH14_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901BA8UL)
#define CYREG_PASS0_SAR1_CH14_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901BB8UL)
#define CYREG_PASS0_SAR1_CH14_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901BBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH15)
  */
#define CYREG_PASS0_SAR1_CH15_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901BC0UL)
#define CYREG_PASS0_SAR1_CH15_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901BC4UL)
#define CYREG_PASS0_SAR1_CH15_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901BC8UL)
#define CYREG_PASS0_SAR1_CH15_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901BCCUL)
#define CYREG_PASS0_SAR1_CH15_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901BD0UL)
#define CYREG_PASS0_SAR1_CH15_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901BD4UL)
#define CYREG_PASS0_SAR1_CH15_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901BD8UL)
#define CYREG_PASS0_SAR1_CH15_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901BDCUL)
#define CYREG_PASS0_SAR1_CH15_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901BE0UL)
#define CYREG_PASS0_SAR1_CH15_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901BE4UL)
#define CYREG_PASS0_SAR1_CH15_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901BE8UL)
#define CYREG_PASS0_SAR1_CH15_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901BF8UL)
#define CYREG_PASS0_SAR1_CH15_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901BFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH16)
  */
#define CYREG_PASS0_SAR1_CH16_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901C00UL)
#define CYREG_PASS0_SAR1_CH16_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901C04UL)
#define CYREG_PASS0_SAR1_CH16_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901C08UL)
#define CYREG_PASS0_SAR1_CH16_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901C0CUL)
#define CYREG_PASS0_SAR1_CH16_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901C10UL)
#define CYREG_PASS0_SAR1_CH16_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901C14UL)
#define CYREG_PASS0_SAR1_CH16_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901C18UL)
#define CYREG_PASS0_SAR1_CH16_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901C1CUL)
#define CYREG_PASS0_SAR1_CH16_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901C20UL)
#define CYREG_PASS0_SAR1_CH16_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901C24UL)
#define CYREG_PASS0_SAR1_CH16_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901C28UL)
#define CYREG_PASS0_SAR1_CH16_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901C38UL)
#define CYREG_PASS0_SAR1_CH16_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901C3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH17)
  */
#define CYREG_PASS0_SAR1_CH17_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901C40UL)
#define CYREG_PASS0_SAR1_CH17_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901C44UL)
#define CYREG_PASS0_SAR1_CH17_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901C48UL)
#define CYREG_PASS0_SAR1_CH17_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901C4CUL)
#define CYREG_PASS0_SAR1_CH17_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901C50UL)
#define CYREG_PASS0_SAR1_CH17_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901C54UL)
#define CYREG_PASS0_SAR1_CH17_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901C58UL)
#define CYREG_PASS0_SAR1_CH17_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901C5CUL)
#define CYREG_PASS0_SAR1_CH17_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901C60UL)
#define CYREG_PASS0_SAR1_CH17_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901C64UL)
#define CYREG_PASS0_SAR1_CH17_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901C68UL)
#define CYREG_PASS0_SAR1_CH17_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901C78UL)
#define CYREG_PASS0_SAR1_CH17_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901C7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH18)
  */
#define CYREG_PASS0_SAR1_CH18_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901C80UL)
#define CYREG_PASS0_SAR1_CH18_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901C84UL)
#define CYREG_PASS0_SAR1_CH18_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901C88UL)
#define CYREG_PASS0_SAR1_CH18_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901C8CUL)
#define CYREG_PASS0_SAR1_CH18_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901C90UL)
#define CYREG_PASS0_SAR1_CH18_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901C94UL)
#define CYREG_PASS0_SAR1_CH18_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901C98UL)
#define CYREG_PASS0_SAR1_CH18_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901C9CUL)
#define CYREG_PASS0_SAR1_CH18_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901CA0UL)
#define CYREG_PASS0_SAR1_CH18_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901CA4UL)
#define CYREG_PASS0_SAR1_CH18_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901CA8UL)
#define CYREG_PASS0_SAR1_CH18_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901CB8UL)
#define CYREG_PASS0_SAR1_CH18_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901CBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH19)
  */
#define CYREG_PASS0_SAR1_CH19_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901CC0UL)
#define CYREG_PASS0_SAR1_CH19_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901CC4UL)
#define CYREG_PASS0_SAR1_CH19_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901CC8UL)
#define CYREG_PASS0_SAR1_CH19_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901CCCUL)
#define CYREG_PASS0_SAR1_CH19_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901CD0UL)
#define CYREG_PASS0_SAR1_CH19_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901CD4UL)
#define CYREG_PASS0_SAR1_CH19_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901CD8UL)
#define CYREG_PASS0_SAR1_CH19_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901CDCUL)
#define CYREG_PASS0_SAR1_CH19_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901CE0UL)
#define CYREG_PASS0_SAR1_CH19_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901CE4UL)
#define CYREG_PASS0_SAR1_CH19_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901CE8UL)
#define CYREG_PASS0_SAR1_CH19_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901CF8UL)
#define CYREG_PASS0_SAR1_CH19_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901CFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH20)
  */
#define CYREG_PASS0_SAR1_CH20_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901D00UL)
#define CYREG_PASS0_SAR1_CH20_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901D04UL)
#define CYREG_PASS0_SAR1_CH20_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901D08UL)
#define CYREG_PASS0_SAR1_CH20_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901D0CUL)
#define CYREG_PASS0_SAR1_CH20_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901D10UL)
#define CYREG_PASS0_SAR1_CH20_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901D14UL)
#define CYREG_PASS0_SAR1_CH20_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901D18UL)
#define CYREG_PASS0_SAR1_CH20_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901D1CUL)
#define CYREG_PASS0_SAR1_CH20_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901D20UL)
#define CYREG_PASS0_SAR1_CH20_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901D24UL)
#define CYREG_PASS0_SAR1_CH20_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901D28UL)
#define CYREG_PASS0_SAR1_CH20_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901D38UL)
#define CYREG_PASS0_SAR1_CH20_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901D3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH21)
  */
#define CYREG_PASS0_SAR1_CH21_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901D40UL)
#define CYREG_PASS0_SAR1_CH21_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901D44UL)
#define CYREG_PASS0_SAR1_CH21_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901D48UL)
#define CYREG_PASS0_SAR1_CH21_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901D4CUL)
#define CYREG_PASS0_SAR1_CH21_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901D50UL)
#define CYREG_PASS0_SAR1_CH21_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901D54UL)
#define CYREG_PASS0_SAR1_CH21_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901D58UL)
#define CYREG_PASS0_SAR1_CH21_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901D5CUL)
#define CYREG_PASS0_SAR1_CH21_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901D60UL)
#define CYREG_PASS0_SAR1_CH21_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901D64UL)
#define CYREG_PASS0_SAR1_CH21_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901D68UL)
#define CYREG_PASS0_SAR1_CH21_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901D78UL)
#define CYREG_PASS0_SAR1_CH21_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901D7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH22)
  */
#define CYREG_PASS0_SAR1_CH22_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901D80UL)
#define CYREG_PASS0_SAR1_CH22_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901D84UL)
#define CYREG_PASS0_SAR1_CH22_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901D88UL)
#define CYREG_PASS0_SAR1_CH22_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901D8CUL)
#define CYREG_PASS0_SAR1_CH22_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901D90UL)
#define CYREG_PASS0_SAR1_CH22_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901D94UL)
#define CYREG_PASS0_SAR1_CH22_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901D98UL)
#define CYREG_PASS0_SAR1_CH22_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901D9CUL)
#define CYREG_PASS0_SAR1_CH22_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901DA0UL)
#define CYREG_PASS0_SAR1_CH22_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901DA4UL)
#define CYREG_PASS0_SAR1_CH22_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901DA8UL)
#define CYREG_PASS0_SAR1_CH22_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901DB8UL)
#define CYREG_PASS0_SAR1_CH22_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901DBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH23)
  */
#define CYREG_PASS0_SAR1_CH23_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901DC0UL)
#define CYREG_PASS0_SAR1_CH23_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901DC4UL)
#define CYREG_PASS0_SAR1_CH23_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901DC8UL)
#define CYREG_PASS0_SAR1_CH23_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901DCCUL)
#define CYREG_PASS0_SAR1_CH23_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901DD0UL)
#define CYREG_PASS0_SAR1_CH23_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901DD4UL)
#define CYREG_PASS0_SAR1_CH23_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901DD8UL)
#define CYREG_PASS0_SAR1_CH23_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901DDCUL)
#define CYREG_PASS0_SAR1_CH23_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901DE0UL)
#define CYREG_PASS0_SAR1_CH23_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901DE4UL)
#define CYREG_PASS0_SAR1_CH23_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901DE8UL)
#define CYREG_PASS0_SAR1_CH23_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901DF8UL)
#define CYREG_PASS0_SAR1_CH23_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901DFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH24)
  */
#define CYREG_PASS0_SAR1_CH24_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901E00UL)
#define CYREG_PASS0_SAR1_CH24_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901E04UL)
#define CYREG_PASS0_SAR1_CH24_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901E08UL)
#define CYREG_PASS0_SAR1_CH24_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901E0CUL)
#define CYREG_PASS0_SAR1_CH24_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901E10UL)
#define CYREG_PASS0_SAR1_CH24_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901E14UL)
#define CYREG_PASS0_SAR1_CH24_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901E18UL)
#define CYREG_PASS0_SAR1_CH24_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901E1CUL)
#define CYREG_PASS0_SAR1_CH24_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901E20UL)
#define CYREG_PASS0_SAR1_CH24_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901E24UL)
#define CYREG_PASS0_SAR1_CH24_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901E28UL)
#define CYREG_PASS0_SAR1_CH24_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901E38UL)
#define CYREG_PASS0_SAR1_CH24_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901E3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH25)
  */
#define CYREG_PASS0_SAR1_CH25_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901E40UL)
#define CYREG_PASS0_SAR1_CH25_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901E44UL)
#define CYREG_PASS0_SAR1_CH25_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901E48UL)
#define CYREG_PASS0_SAR1_CH25_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901E4CUL)
#define CYREG_PASS0_SAR1_CH25_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901E50UL)
#define CYREG_PASS0_SAR1_CH25_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901E54UL)
#define CYREG_PASS0_SAR1_CH25_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901E58UL)
#define CYREG_PASS0_SAR1_CH25_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901E5CUL)
#define CYREG_PASS0_SAR1_CH25_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901E60UL)
#define CYREG_PASS0_SAR1_CH25_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901E64UL)
#define CYREG_PASS0_SAR1_CH25_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901E68UL)
#define CYREG_PASS0_SAR1_CH25_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901E78UL)
#define CYREG_PASS0_SAR1_CH25_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901E7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH26)
  */
#define CYREG_PASS0_SAR1_CH26_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901E80UL)
#define CYREG_PASS0_SAR1_CH26_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901E84UL)
#define CYREG_PASS0_SAR1_CH26_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901E88UL)
#define CYREG_PASS0_SAR1_CH26_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901E8CUL)
#define CYREG_PASS0_SAR1_CH26_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901E90UL)
#define CYREG_PASS0_SAR1_CH26_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901E94UL)
#define CYREG_PASS0_SAR1_CH26_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901E98UL)
#define CYREG_PASS0_SAR1_CH26_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901E9CUL)
#define CYREG_PASS0_SAR1_CH26_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901EA0UL)
#define CYREG_PASS0_SAR1_CH26_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901EA4UL)
#define CYREG_PASS0_SAR1_CH26_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901EA8UL)
#define CYREG_PASS0_SAR1_CH26_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901EB8UL)
#define CYREG_PASS0_SAR1_CH26_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901EBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH27)
  */
#define CYREG_PASS0_SAR1_CH27_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901EC0UL)
#define CYREG_PASS0_SAR1_CH27_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901EC4UL)
#define CYREG_PASS0_SAR1_CH27_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901EC8UL)
#define CYREG_PASS0_SAR1_CH27_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901ECCUL)
#define CYREG_PASS0_SAR1_CH27_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901ED0UL)
#define CYREG_PASS0_SAR1_CH27_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901ED4UL)
#define CYREG_PASS0_SAR1_CH27_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901ED8UL)
#define CYREG_PASS0_SAR1_CH27_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901EDCUL)
#define CYREG_PASS0_SAR1_CH27_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901EE0UL)
#define CYREG_PASS0_SAR1_CH27_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901EE4UL)
#define CYREG_PASS0_SAR1_CH27_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901EE8UL)
#define CYREG_PASS0_SAR1_CH27_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901EF8UL)
#define CYREG_PASS0_SAR1_CH27_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901EFCUL)

/**
  * \brief Channel structure (PASS_SAR_CH28)
  */
#define CYREG_PASS0_SAR1_CH28_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901F00UL)
#define CYREG_PASS0_SAR1_CH28_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901F04UL)
#define CYREG_PASS0_SAR1_CH28_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901F08UL)
#define CYREG_PASS0_SAR1_CH28_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901F0CUL)
#define CYREG_PASS0_SAR1_CH28_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901F10UL)
#define CYREG_PASS0_SAR1_CH28_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901F14UL)
#define CYREG_PASS0_SAR1_CH28_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901F18UL)
#define CYREG_PASS0_SAR1_CH28_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901F1CUL)
#define CYREG_PASS0_SAR1_CH28_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901F20UL)
#define CYREG_PASS0_SAR1_CH28_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901F24UL)
#define CYREG_PASS0_SAR1_CH28_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901F28UL)
#define CYREG_PASS0_SAR1_CH28_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901F38UL)
#define CYREG_PASS0_SAR1_CH28_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901F3CUL)

/**
  * \brief Channel structure (PASS_SAR_CH29)
  */
#define CYREG_PASS0_SAR1_CH29_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901F40UL)
#define CYREG_PASS0_SAR1_CH29_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901F44UL)
#define CYREG_PASS0_SAR1_CH29_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901F48UL)
#define CYREG_PASS0_SAR1_CH29_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901F4CUL)
#define CYREG_PASS0_SAR1_CH29_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901F50UL)
#define CYREG_PASS0_SAR1_CH29_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901F54UL)
#define CYREG_PASS0_SAR1_CH29_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901F58UL)
#define CYREG_PASS0_SAR1_CH29_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901F5CUL)
#define CYREG_PASS0_SAR1_CH29_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901F60UL)
#define CYREG_PASS0_SAR1_CH29_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901F64UL)
#define CYREG_PASS0_SAR1_CH29_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901F68UL)
#define CYREG_PASS0_SAR1_CH29_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901F78UL)
#define CYREG_PASS0_SAR1_CH29_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901F7CUL)

/**
  * \brief Channel structure (PASS_SAR_CH30)
  */
#define CYREG_PASS0_SAR1_CH30_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901F80UL)
#define CYREG_PASS0_SAR1_CH30_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901F84UL)
#define CYREG_PASS0_SAR1_CH30_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901F88UL)
#define CYREG_PASS0_SAR1_CH30_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901F8CUL)
#define CYREG_PASS0_SAR1_CH30_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901F90UL)
#define CYREG_PASS0_SAR1_CH30_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901F94UL)
#define CYREG_PASS0_SAR1_CH30_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901F98UL)
#define CYREG_PASS0_SAR1_CH30_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901F9CUL)
#define CYREG_PASS0_SAR1_CH30_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901FA0UL)
#define CYREG_PASS0_SAR1_CH30_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901FA4UL)
#define CYREG_PASS0_SAR1_CH30_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901FA8UL)
#define CYREG_PASS0_SAR1_CH30_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901FB8UL)
#define CYREG_PASS0_SAR1_CH30_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901FBCUL)

/**
  * \brief Channel structure (PASS_SAR_CH31)
  */
#define CYREG_PASS0_SAR1_CH31_TR_CTL    ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40901FC0UL)
#define CYREG_PASS0_SAR1_CH31_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40901FC4UL)
#define CYREG_PASS0_SAR1_CH31_POST_CTL  ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40901FC8UL)
#define CYREG_PASS0_SAR1_CH31_RANGE_CTL ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x40901FCCUL)
#define CYREG_PASS0_SAR1_CH31_INTR      ((volatile un_PASS_SAR_CH_INTR_t*) 0x40901FD0UL)
#define CYREG_PASS0_SAR1_CH31_INTR_SET  ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40901FD4UL)
#define CYREG_PASS0_SAR1_CH31_INTR_MASK ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40901FD8UL)
#define CYREG_PASS0_SAR1_CH31_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x40901FDCUL)
#define CYREG_PASS0_SAR1_CH31_WORK      ((volatile un_PASS_SAR_CH_WORK_t*) 0x40901FE0UL)
#define CYREG_PASS0_SAR1_CH31_RESULT    ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40901FE4UL)
#define CYREG_PASS0_SAR1_CH31_GRP_STAT  ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40901FE8UL)
#define CYREG_PASS0_SAR1_CH31_ENABLE    ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40901FF8UL)
#define CYREG_PASS0_SAR1_CH31_TR_CMD    ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x40901FFCUL)

/**
  * \brief SAR ADC with Sequencer for S40E (PASS_SAR1)
  */
#define CYREG_PASS0_SAR1_CTL            ((volatile un_PASS_SAR_CTL_t*) 0x40901000UL)
#define CYREG_PASS0_SAR1_DIAG_CTL       ((volatile un_PASS_SAR_DIAG_CTL_t*) 0x40901004UL)
#define CYREG_PASS0_SAR1_PRECOND_CTL    ((volatile un_PASS_SAR_PRECOND_CTL_t*) 0x40901010UL)
#define CYREG_PASS0_SAR1_ANA_CAL        ((volatile un_PASS_SAR_ANA_CAL_t*) 0x40901080UL)
#define CYREG_PASS0_SAR1_DIG_CAL        ((volatile un_PASS_SAR_DIG_CAL_t*) 0x40901084UL)
#define CYREG_PASS0_SAR1_ANA_CAL_ALT    ((volatile un_PASS_SAR_ANA_CAL_ALT_t*) 0x40901090UL)
#define CYREG_PASS0_SAR1_DIG_CAL_ALT    ((volatile un_PASS_SAR_DIG_CAL_ALT_t*) 0x40901094UL)
#define CYREG_PASS0_SAR1_CAL_UPD_CMD    ((volatile un_PASS_SAR_CAL_UPD_CMD_t*) 0x40901098UL)
#define CYREG_PASS0_SAR1_TR_PEND        ((volatile un_PASS_SAR_TR_PEND_t*) 0x40901100UL)
#define CYREG_PASS0_SAR1_WORK_VALID     ((volatile un_PASS_SAR_WORK_VALID_t*) 0x40901180UL)
#define CYREG_PASS0_SAR1_WORK_RANGE     ((volatile un_PASS_SAR_WORK_RANGE_t*) 0x40901184UL)
#define CYREG_PASS0_SAR1_WORK_RANGE_HI  ((volatile un_PASS_SAR_WORK_RANGE_HI_t*) 0x40901188UL)
#define CYREG_PASS0_SAR1_WORK_PULSE     ((volatile un_PASS_SAR_WORK_PULSE_t*) 0x4090118CUL)
#define CYREG_PASS0_SAR1_RESULT_VALID   ((volatile un_PASS_SAR_RESULT_VALID_t*) 0x409011A0UL)
#define CYREG_PASS0_SAR1_RESULT_RANGE_HI ((volatile un_PASS_SAR_RESULT_RANGE_HI_t*) 0x409011A4UL)
#define CYREG_PASS0_SAR1_STATUS         ((volatile un_PASS_SAR_STATUS_t*) 0x40901200UL)
#define CYREG_PASS0_SAR1_AVG_STAT       ((volatile un_PASS_SAR_AVG_STAT_t*) 0x40901204UL)

/**
  * \brief Channel structure (PASS_SAR_CH0)
  */
#define CYREG_PASS0_SAR2_CH0_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902800UL)
#define CYREG_PASS0_SAR2_CH0_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902804UL)
#define CYREG_PASS0_SAR2_CH0_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902808UL)
#define CYREG_PASS0_SAR2_CH0_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090280CUL)
#define CYREG_PASS0_SAR2_CH0_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902810UL)
#define CYREG_PASS0_SAR2_CH0_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902814UL)
#define CYREG_PASS0_SAR2_CH0_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902818UL)
#define CYREG_PASS0_SAR2_CH0_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090281CUL)
#define CYREG_PASS0_SAR2_CH0_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40902820UL)
#define CYREG_PASS0_SAR2_CH0_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40902824UL)
#define CYREG_PASS0_SAR2_CH0_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40902828UL)
#define CYREG_PASS0_SAR2_CH0_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40902838UL)
#define CYREG_PASS0_SAR2_CH0_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090283CUL)

/**
  * \brief Channel structure (PASS_SAR_CH1)
  */
#define CYREG_PASS0_SAR2_CH1_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902840UL)
#define CYREG_PASS0_SAR2_CH1_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902844UL)
#define CYREG_PASS0_SAR2_CH1_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902848UL)
#define CYREG_PASS0_SAR2_CH1_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090284CUL)
#define CYREG_PASS0_SAR2_CH1_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902850UL)
#define CYREG_PASS0_SAR2_CH1_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902854UL)
#define CYREG_PASS0_SAR2_CH1_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902858UL)
#define CYREG_PASS0_SAR2_CH1_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090285CUL)
#define CYREG_PASS0_SAR2_CH1_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40902860UL)
#define CYREG_PASS0_SAR2_CH1_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40902864UL)
#define CYREG_PASS0_SAR2_CH1_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40902868UL)
#define CYREG_PASS0_SAR2_CH1_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40902878UL)
#define CYREG_PASS0_SAR2_CH1_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090287CUL)

/**
  * \brief Channel structure (PASS_SAR_CH2)
  */
#define CYREG_PASS0_SAR2_CH2_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902880UL)
#define CYREG_PASS0_SAR2_CH2_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902884UL)
#define CYREG_PASS0_SAR2_CH2_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902888UL)
#define CYREG_PASS0_SAR2_CH2_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090288CUL)
#define CYREG_PASS0_SAR2_CH2_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902890UL)
#define CYREG_PASS0_SAR2_CH2_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902894UL)
#define CYREG_PASS0_SAR2_CH2_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902898UL)
#define CYREG_PASS0_SAR2_CH2_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090289CUL)
#define CYREG_PASS0_SAR2_CH2_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409028A0UL)
#define CYREG_PASS0_SAR2_CH2_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409028A4UL)
#define CYREG_PASS0_SAR2_CH2_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409028A8UL)
#define CYREG_PASS0_SAR2_CH2_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409028B8UL)
#define CYREG_PASS0_SAR2_CH2_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409028BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH3)
  */
#define CYREG_PASS0_SAR2_CH3_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409028C0UL)
#define CYREG_PASS0_SAR2_CH3_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409028C4UL)
#define CYREG_PASS0_SAR2_CH3_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409028C8UL)
#define CYREG_PASS0_SAR2_CH3_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409028CCUL)
#define CYREG_PASS0_SAR2_CH3_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409028D0UL)
#define CYREG_PASS0_SAR2_CH3_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409028D4UL)
#define CYREG_PASS0_SAR2_CH3_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409028D8UL)
#define CYREG_PASS0_SAR2_CH3_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409028DCUL)
#define CYREG_PASS0_SAR2_CH3_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409028E0UL)
#define CYREG_PASS0_SAR2_CH3_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409028E4UL)
#define CYREG_PASS0_SAR2_CH3_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409028E8UL)
#define CYREG_PASS0_SAR2_CH3_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409028F8UL)
#define CYREG_PASS0_SAR2_CH3_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409028FCUL)

/**
  * \brief Channel structure (PASS_SAR_CH4)
  */
#define CYREG_PASS0_SAR2_CH4_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902900UL)
#define CYREG_PASS0_SAR2_CH4_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902904UL)
#define CYREG_PASS0_SAR2_CH4_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902908UL)
#define CYREG_PASS0_SAR2_CH4_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090290CUL)
#define CYREG_PASS0_SAR2_CH4_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902910UL)
#define CYREG_PASS0_SAR2_CH4_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902914UL)
#define CYREG_PASS0_SAR2_CH4_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902918UL)
#define CYREG_PASS0_SAR2_CH4_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090291CUL)
#define CYREG_PASS0_SAR2_CH4_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40902920UL)
#define CYREG_PASS0_SAR2_CH4_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40902924UL)
#define CYREG_PASS0_SAR2_CH4_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40902928UL)
#define CYREG_PASS0_SAR2_CH4_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40902938UL)
#define CYREG_PASS0_SAR2_CH4_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090293CUL)

/**
  * \brief Channel structure (PASS_SAR_CH5)
  */
#define CYREG_PASS0_SAR2_CH5_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902940UL)
#define CYREG_PASS0_SAR2_CH5_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902944UL)
#define CYREG_PASS0_SAR2_CH5_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902948UL)
#define CYREG_PASS0_SAR2_CH5_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090294CUL)
#define CYREG_PASS0_SAR2_CH5_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902950UL)
#define CYREG_PASS0_SAR2_CH5_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902954UL)
#define CYREG_PASS0_SAR2_CH5_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902958UL)
#define CYREG_PASS0_SAR2_CH5_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090295CUL)
#define CYREG_PASS0_SAR2_CH5_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x40902960UL)
#define CYREG_PASS0_SAR2_CH5_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x40902964UL)
#define CYREG_PASS0_SAR2_CH5_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x40902968UL)
#define CYREG_PASS0_SAR2_CH5_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x40902978UL)
#define CYREG_PASS0_SAR2_CH5_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x4090297CUL)

/**
  * \brief Channel structure (PASS_SAR_CH6)
  */
#define CYREG_PASS0_SAR2_CH6_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x40902980UL)
#define CYREG_PASS0_SAR2_CH6_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x40902984UL)
#define CYREG_PASS0_SAR2_CH6_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x40902988UL)
#define CYREG_PASS0_SAR2_CH6_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x4090298CUL)
#define CYREG_PASS0_SAR2_CH6_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x40902990UL)
#define CYREG_PASS0_SAR2_CH6_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x40902994UL)
#define CYREG_PASS0_SAR2_CH6_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x40902998UL)
#define CYREG_PASS0_SAR2_CH6_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x4090299CUL)
#define CYREG_PASS0_SAR2_CH6_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409029A0UL)
#define CYREG_PASS0_SAR2_CH6_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409029A4UL)
#define CYREG_PASS0_SAR2_CH6_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409029A8UL)
#define CYREG_PASS0_SAR2_CH6_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409029B8UL)
#define CYREG_PASS0_SAR2_CH6_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409029BCUL)

/**
  * \brief Channel structure (PASS_SAR_CH7)
  */
#define CYREG_PASS0_SAR2_CH7_TR_CTL     ((volatile un_PASS_SAR_CH_TR_CTL_t*) 0x409029C0UL)
#define CYREG_PASS0_SAR2_CH7_SAMPLE_CTL ((volatile un_PASS_SAR_CH_SAMPLE_CTL_t*) 0x409029C4UL)
#define CYREG_PASS0_SAR2_CH7_POST_CTL   ((volatile un_PASS_SAR_CH_POST_CTL_t*) 0x409029C8UL)
#define CYREG_PASS0_SAR2_CH7_RANGE_CTL  ((volatile un_PASS_SAR_CH_RANGE_CTL_t*) 0x409029CCUL)
#define CYREG_PASS0_SAR2_CH7_INTR       ((volatile un_PASS_SAR_CH_INTR_t*) 0x409029D0UL)
#define CYREG_PASS0_SAR2_CH7_INTR_SET   ((volatile un_PASS_SAR_CH_INTR_SET_t*) 0x409029D4UL)
#define CYREG_PASS0_SAR2_CH7_INTR_MASK  ((volatile un_PASS_SAR_CH_INTR_MASK_t*) 0x409029D8UL)
#define CYREG_PASS0_SAR2_CH7_INTR_MASKED ((volatile un_PASS_SAR_CH_INTR_MASKED_t*) 0x409029DCUL)
#define CYREG_PASS0_SAR2_CH7_WORK       ((volatile un_PASS_SAR_CH_WORK_t*) 0x409029E0UL)
#define CYREG_PASS0_SAR2_CH7_RESULT     ((volatile un_PASS_SAR_CH_RESULT_t*) 0x409029E4UL)
#define CYREG_PASS0_SAR2_CH7_GRP_STAT   ((volatile un_PASS_SAR_CH_GRP_STAT_t*) 0x409029E8UL)
#define CYREG_PASS0_SAR2_CH7_ENABLE     ((volatile un_PASS_SAR_CH_ENABLE_t*) 0x409029F8UL)
#define CYREG_PASS0_SAR2_CH7_TR_CMD     ((volatile un_PASS_SAR_CH_TR_CMD_t*) 0x409029FCUL)

/**
  * \brief SAR ADC with Sequencer for S40E (PASS_SAR2)
  */
#define CYREG_PASS0_SAR2_CTL            ((volatile un_PASS_SAR_CTL_t*) 0x40902000UL)
#define CYREG_PASS0_SAR2_DIAG_CTL       ((volatile un_PASS_SAR_DIAG_CTL_t*) 0x40902004UL)
#define CYREG_PASS0_SAR2_PRECOND_CTL    ((volatile un_PASS_SAR_PRECOND_CTL_t*) 0x40902010UL)
#define CYREG_PASS0_SAR2_ANA_CAL        ((volatile un_PASS_SAR_ANA_CAL_t*) 0x40902080UL)
#define CYREG_PASS0_SAR2_DIG_CAL        ((volatile un_PASS_SAR_DIG_CAL_t*) 0x40902084UL)
#define CYREG_PASS0_SAR2_ANA_CAL_ALT    ((volatile un_PASS_SAR_ANA_CAL_ALT_t*) 0x40902090UL)
#define CYREG_PASS0_SAR2_DIG_CAL_ALT    ((volatile un_PASS_SAR_DIG_CAL_ALT_t*) 0x40902094UL)
#define CYREG_PASS0_SAR2_CAL_UPD_CMD    ((volatile un_PASS_SAR_CAL_UPD_CMD_t*) 0x40902098UL)
#define CYREG_PASS0_SAR2_TR_PEND        ((volatile un_PASS_SAR_TR_PEND_t*) 0x40902100UL)
#define CYREG_PASS0_SAR2_WORK_VALID     ((volatile un_PASS_SAR_WORK_VALID_t*) 0x40902180UL)
#define CYREG_PASS0_SAR2_WORK_RANGE     ((volatile un_PASS_SAR_WORK_RANGE_t*) 0x40902184UL)
#define CYREG_PASS0_SAR2_WORK_RANGE_HI  ((volatile un_PASS_SAR_WORK_RANGE_HI_t*) 0x40902188UL)
#define CYREG_PASS0_SAR2_WORK_PULSE     ((volatile un_PASS_SAR_WORK_PULSE_t*) 0x4090218CUL)
#define CYREG_PASS0_SAR2_RESULT_VALID   ((volatile un_PASS_SAR_RESULT_VALID_t*) 0x409021A0UL)
#define CYREG_PASS0_SAR2_RESULT_RANGE_HI ((volatile un_PASS_SAR_RESULT_RANGE_HI_t*) 0x409021A4UL)
#define CYREG_PASS0_SAR2_STATUS         ((volatile un_PASS_SAR_STATUS_t*) 0x40902200UL)
#define CYREG_PASS0_SAR2_AVG_STAT       ((volatile un_PASS_SAR_AVG_STAT_t*) 0x40902204UL)

/**
  * \brief PASS top-level MMIO (Generic Triggers) (PASS_EPASS_MMIO0)
  */
#define CYREG_PASS0_PASS_CTL            ((volatile un_PASS_PASS_CTL_t*) 0x409F0000UL)
#define CYREG_PASS0_SAR_TR_IN_SEL0      ((volatile un_PASS_SAR_TR_IN_SEL_t*) 0x409F0020UL)
#define CYREG_PASS0_SAR_TR_IN_SEL1      ((volatile un_PASS_SAR_TR_IN_SEL_t*) 0x409F0024UL)
#define CYREG_PASS0_SAR_TR_IN_SEL2      ((volatile un_PASS_SAR_TR_IN_SEL_t*) 0x409F0028UL)
#define CYREG_PASS0_SAR_TR_OUT_SEL0     ((volatile un_PASS_SAR_TR_OUT_SEL_t*) 0x409F0040UL)
#define CYREG_PASS0_SAR_TR_OUT_SEL1     ((volatile un_PASS_SAR_TR_OUT_SEL_t*) 0x409F0044UL)
#define CYREG_PASS0_SAR_TR_OUT_SEL2     ((volatile un_PASS_SAR_TR_OUT_SEL_t*) 0x409F0048UL)

#endif /* _CYREG_PASS_H_ */


/* [] END OF FILE */
